The present invention relates in general to organizing transaction requests in a computing device or system, and more specifically, to aggregating/fusing transaction requests of the same type that request access to contiguous lines of memory.
In computer architecture, a memory hierarchy is used to visualize and address performance issues in computer architectural design, algorithm predictions, and lower level programming. The memory hierarchy separates each hierarchy level based on response time.
Computer systems, processors, caches, I/O device and other devices in the computer architecture access data in memory using one or more memory controllers. The memory controllers manage the movement of data to and from memory, for example, a dynamic random access memory (DRAM). In some computer systems, an electronic transaction message is a request to access a memory location in memory.